In the DRAM industry, as DRAMs increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally there is a continuing goal to further decrease cell area. Generally, the capacitance of the capacitor directly related to the surface area of the capacitor. For this reason, there is continuous challenge to increase the surface area of the capacitor, i.e., conventional two-dimensional structure to three-dimensional structure(trench or stacked capacitor). The widely adopted stacked capacitor includes for example cylindrical and fin type capacitor.
From the fabrication sequence point view, the structure of the capacitor mainly classified into COB(capacitor over bit line) structure and CUB(capacitor under bit line) structure. The significant difference between them is the time when the capacitor is formed, i.e., after forming the bit line(COB) or before forming the bit line(CUB).
The COB structure has an advantage that the capacitor can be formed without regard to the bit line process margin since the capacitor is formed after the bit line formation. Therefore, it has a relatively increased capacitance in comparison with the CUB structure. On the contrary, in the COB structure, the bit line design rule put a limit on process margin for buried contacts formation for electrical connection to storage electrode and switch transistor.
FIG. 1 is a cross-sectional view showing a conventional DRAM structure. In the method for fabricating the conventional DRAM structure shown in FIG. 1, a bit line 130 in a cell array region is made of conductive material and at the same time(i.e., at the same process step) an interconnection wiring line 130a in core/peripheral region are formed by using the same conductive material as the bit line. By doing this, the conventional method can simplify the process and reduce the cost. Capping layers 132 and 134 for example silicon nitride layer(Si.sub.3 N.sub.4) are formed to coat exposed portion of the bit line 130 and the interconnection wiring line 130a so as to protect the bit line 130 and the interconnection wiring line 130a during subsequent etching process. After that, lower electrode 136(i.e., storage electrode) of the capacitor, dielectric film, and upper electrode 140 (i.e., plate electrode) are sequentially formed.
Herein, the step of forming the storage electrode 136 includes depositing a conductive material over the semiconductor substrate and etching the conductive material to form the storage electrode 136 using predetermined pattern. Because the conductive material in the core/peripheral region must be completely removed away, over etch can be conducted. Therefore, in the step of etching the conductive material, the capping layers 132 and 134 in the core/peripheral region can be etched and further in the steps of forming the dielectric film and the plate electrode 140 can be etched, thereby causing open fail of the interconnection wiring line 130a. But also, in the case of reducing the etching rate in the core/peripheral region so as to overcome above problems, material residues occurs between the bit lines 130 or the interconnection wiring lines 130a, thereby making it difficult to form contact hole.